caching - Cache miss on a multilevel cache -


there 2 levels of cache l1 , l2. if there cache miss on both levels, data being read memory. during reading data main memory, data first entered l2 , l1 cache first , processor reads data l1 cache or updation l1 , l2 , read processor happen simultaneously?

i believe depends on hardware implementation. think depends on whether or not write-through or write-back cache. write through have same data @ levels because updates @ same time. put write buffer written cache, in case happen @ same time read. if there no write buffer, processor might stall allow cache updated.


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