fpga - VHDL: converting an std_logic_vector to an integer (works in simulation, not practice) -

the past 2 days have been fighting 1 problem. want data_out send "111" in case, seeing how entire memory filled '1'. show code , make question more precise:

entity tile_library   port (     data_out : out std_logic_vector(2 downto 0);     data_in : in std_logic_vector(5 downto 0);     clk : in std_logic);  end tile_library;  architecture behavioral of tile_library  type memory_type array (0 63) of std_logic_vector(255 downto 0); signal memory : memory_type := (others=> (others=>'1')); signal something_to_convert : std_logic_vector(5 downto 0) := "000000";   begin   process(clk) begin   if rising_edge(clk)     if memory(to_integer(unsigned(data_in)))(5) = '1'       data_out <= "111";     else       data_out <= "000";     end if;    end if; end process;   end behavioral; 

if replace

    if memory(to_integer(unsigned(data_in)))(5) = '1' 

with

    if memory(to_integer(unsigned(something_to_convert)))(5) = '1' 

i "111" output on nexys 3 card.

this leads me believe data_in not should be.

therefore, show code yields data_in tile_library in tests:

entity tile_memory   port (     data_out : out std_logic_vector(5 downto 0);     clk : in std_logic);  end tile_memory;  architecture behavioral of tile_memory  begin   process(clk)   begin    if rising_edge(clk)      data_out <= "000000";     end if;   end process;  end behavioral; 

to further confusion, add according simulations, exact same in , out signals (which correct ones, "111") both if memory(to_integer(unsigned(data_in)))(5) = '1' then , if memory(to_integer(unsigned(something_to_convert)))(5) = '1' then. when run on nexys 3 card; however, yield different results.

what doing wrong here?

there nothing wrong with

signal memory : memory_type := (others=> (others=>'1')); 

in xilinx software works me time.

i'd suggest using chipscope , place keep/mark_debug attribute on signals want view because others point out optimized out. doesn't mean should getting wrong result.

data_out should "000" (due xilinx synthesis assumption) first clock cycle "111" consecutive clock cycles.

if synthesis stuffing guess doesn't ram operation part of if statement (i've never seen before). try taking out of if statement (as shown below). should not required xst can rather sensitive when comes recognizing memory/multipliers etc.

you can look @ post synthesis schematic/simulation suggest chipscope first.

entity tile_library   port (     data_out : out std_logic_vector(2 downto 0);     data_in : in std_logic_vector(5 downto 0);     clk : in std_logic);  end tile_library;  architecture behavioral of tile_library  type memory_type array (0 63) of std_logic_vector(255 downto 0); signal memory : memory_type := (others=> (others=>'1')); signal something_to_convert : std_logic_vector(5 downto 0) := "000000"; signal memory_read_data : std_logic_vector(255 downto 0);  begin   memory_read_data <= memory(to_integer(unsigned(data_in)));   process(clk) begin   if rising_edge(clk)     if memory_read_data(5) = '1'       data_out <= "111";     else       data_out <= "000";     end if;    end if; end process;   end behavioral;