Creating a real-time delay in Vhdl -

i want write design in , process gets activated after 1 minute.

i have created 1 more process create delay using counter incrementation, , toggling signal , , giving signal in sensitivity list of process has delayed.

signal delay_over : std_logic;  process ( delay_over ) begin       if clk'event , clk '1'          --design      end if; end process;  delay:process ( clk ) variable counter : integer := 0; begin  --design create delay end process; 

what value or , type of counter should use create delay of exact 1 minute.

equating real time delay in synchronous design (any design clock) is simple counting clocks, or counting enables of time base generated counting clocks.

for example, smallest unit of real time need deal 1 second (that is, never need deal tenths, milliseconds, etc). timebase can seconds. so need figure out how convert period (duration) of single clock second.

let's assume have 25mhz clock. means there 25e6 clocks in second. means need count 25e6 (or (25e6)-1, depending how set up), reset counter zero, , begin counting again. every time counter reaches 0 (or 25e6, or other single value in count), can pulse enable 1 clock cycle. that enable "seconds" timebase.

all other logic can referenced "seconds" timebase enable. create realtime delay of 10 seconds, need count 10 pulses of seconds timebase enable.

here snippet of example, give idea:

   timebase : process (i_clk)    begin       if (rising_edge(i_clk))          counter_1sec_en <= '0';          if (counter < counts_in_1_sec-1)             counter <= counter + 1;          else             counter_1sec_en <= '1';             counter         <= (others => '0');          end if;       end if;    end process timebase;     delay : process (i_clk)    begin       if (rising_edge(i_clk))          seconds_delay_done <= '0';          if (counter_1sec_en = '1')             if (seconds_delay < num_seconds_to_delay-1)                seconds_delay <= seconds_delay + 1;             else                seconds_delay_done <= '1';                seconds_delay <= (others => '0');             end if;          end if;       end if;    end process delay; 

some notes go snippet:

• everything synchronous clock, i_clk
• counts_in_1_sec constant clock frequency in hz
• counter_1sec_en pulses once every second, single i_clk cycle
• num_seconds_to_delay number of seconds want delay. example, 60 seconds.
• seconds_delay_done pulses 1 i_clk cycle when delay has completed.
• you need more control on when arm/enable delay, , possibly control on how many seconds delay (i.e. num_seconds_to_delay may not constant).

in case, if want "activated" after 1 minute, can use seconds_delay_done enable "kick off" whatever want start.

also, see identical answer different question: https://stackoverflow.com/a/29948250/561560