xilinx ise - Square Waveform Generation in VHDL -

i'm working on stopwatch project in vhdl don't know how make clk square waveform of counter? please help.

here code:

library ieee; use ieee.std_logic_1164.all; use ieee.std_logic_unsigned.all;   entity circuit     port ( clk : in  std_logic := '0';            clr : in  std_logic;            q : out  std_logic_vector (5 downto 0)); end circuit;  architecture behavioral of circuit  signal s: std_logic_vector := "000000";  begin  process (clk, clr) begin if rising_edge(clk) if clr = '1' or s = "111011" s <= "000000"; else s <= s+1; end if; end if; end process; q <= s; end behavioral; 

let's clock 1 mhz, want seconds counter process work @ 1 hz. need divide incoming clock 1 million.

constant clock_divider : integer := 1000000; signal clock_divide_counter : integer range 0 clock_divider-1 := 0; signal one_hz_pulse : std_logic := '0'; 

...

process (clk) begin     if (rising_edge(clk))         if (clock_divide_counter = clock_divider - 1)             clock_divide_counter <= 0;             one_hz_pulse <= '1';         else             clock_divide_counter <= clock_divide_counter + 1;             one_hz_pulse <= '0';         end if;     end if; end process; 

then modify existing process enabled when 1 hz pulse high:

process (clk, clr) begin     if rising_edge(clk)         if (clr = '1')             s <= "000000";         elsif (one_hz_pulse = '1')             if s = "111011"                 s <= "000000";             else                 s <= s+1;             end if;         end if;     end if; end process; 

i haven't run code, should idea.