how to read a 32 bit std_logic_vector data from a text file in VHDL -


i want read 32bit signed number text file , store in variable. have program integer read not working std_logic_vector type.

with vhdl-2008, can done like:

library ieee; use ieee.std_logic_1164.all; use std.textio.all;  architecture syn of tb begin   process     file txt_file   : text;     variable line_v : line;     variable slv_v  : std_logic_vector(31 downto 0);     variable good_v : boolean;   begin     -- write text file std_logic_vector     file_open(txt_file, "test.txt", write_mode);     slv_v := x"1234" & "xxxxxxxx" & "zzzzzzzz" ;     write(line_v, slv_v);     writeline(txt_file, line_v);     file_close(txt_file);     -- read text file std_logic_vector     file_open(txt_file, "test.txt", read_mode);     readline(txt_file, line_v);     report "line_v: " & line_v.all;     read(line_v, slv_v, good_v);     file_close(txt_file);     -- done     wait;   end process; end architecture;

the "test.txt" text file contains:

0001001000110100xxxxxxxxzzzzzzzz

with vhdl-2002, std_logic_vector not supported in write/read procedures, synopsys package ieee.std_logic_textio can used provide procedures with:

use ieee.std_logic_textio.all;

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