counter - How to set a value at moduleEN - VHDL -

i've code:

library ieee;  use ieee.std_logic_1164.all;  entity controller port (     clk : in std_logic;     outenable : out std_logic_vector (2 downto 0);     modulereset : in std_logic;     moduleenable : in std_logic ); end controller;  architecture controller_archi of controller     signal counter : integer range 0 4200 := 0;      begin         process (clk, modulereset)         begin             if modulereset = '0'                 outenable <= (others => '0');                 counter <= 0;             elsif rising_edge(clk)                 if moduleenable = '1'                     counter <= counter + 1;                     case counter                         when 0 =>                             outenable <= "001";                         when 450 =>                             outenable <= "010";                         when 900 =>                             outenable <= "100";                         when 1350 =>                             outenable <= "001";                             counter <= 0;                         when others =>                     end case;                 else                     outenable <= "000";                 end if;             end if;         end process;  end controller_archi; 

but it's not working need.

what need:

• when moduleenable goes '1' instantly outenable goes "001" , not @ first rising_edge(clk) (now, in code, if moduleenable goes '1' outenable doesn't change "000" "001", change "001" after first rising_edge(clk))
• counter go when rising_edge(clk) , outenable it's updated every clk event. (now, in code, counter go when rising_edge(clk) outenable it's updated when rising_edge(clk) , not when clk goes , goes down)

so i've modified code that:

library ieee; use ieee.std_logic_1164.all;  entity controller port (     clk : in std_logic;     outenable : out std_logic_vector (2 downto 0);     modulereset : in std_logic;     moduleenable : in std_logic ); end controller;  architecture controller_archi of controller     signal counter : integer range 0 4200 := 0;      begin         process (clk, moduleenable, modulereset)         begin             if modulereset = '0'                 outenable <= (others => '0');                 counter <= 0;             elsif moduleenable = '1'                 if rising_edge(clk)                     counter <= counter + 1;                 end if;                     case counter                         when 0 =>                             outenable <= "001";                         when 450 =>                             outenable <= "010";                         when 900 =>                             outenable <= "100";                         when 1350 =>                             outenable <= "001";                             counter <= 0;                         when others =>                     end case;              else                  counter <= 0;                  outenable <= "000";              end if;         end process;  end controller_archi; 

now code work need in modelsim, when synthesize or compile , simulate again doesn't work.

my question is:

• what it's wrong second code , how can fix it?

• if can't fix second code how can modify first code work need?

what it's wrong second code , how can fix it?

your synthesis tool fussy how clock , reset lines connected. have use structure like:

        if modulereset = '0'            ...         elsif rising_edge(clk) 

or synthesis tool cannot recognise clock , reset lines.

if can't fix second code how can modify first code work need?

you need move "outenable" outside of first process, , process of own. you've said, outenable should not register - should combinatorial function of counter, modulereset , moduleenable. try this.

    process (clk, modulereset)     begin         if modulereset = '0'             counter <= 0;         elsif rising_edge(clk)             if moduleenable = '1'                 counter <= counter + 1;                 case counter                     when 1350 =>                        counter <= 0;                     when others =>                        null;                 end case;             end if;         end if;     end process;      process (counter, modulereset, moduleenable)     begin         outenable <= "000";         if modulereset = '1' , moduleenable = '1'             case counter                 when 0 .. 449 =>                     outenable <= "001";                 when 450 .. 899 =>                     outenable <= "010";                 when 900 .. 1349 =>                     outenable <= "100";                 when others =>                     outenable <= "001";             end case;         end if;     end process;