vhdl - Floating point to fixed point coversion -

i'm creating hardware module using fixed point computations. input floating point, , wish convert floating point input fixed point (q8.8).

i've been trying use david bishops library (http://vhdl.org/fphdl/) floating points , fixed point. works in simulation, not when synthesize it. e.g. in following code output y routed ground when synthesized.

library ieee; use ieee.std_logic_1164.all; use ieee.numeric_std.all; library ieee_proposed; use ieee_proposed.fixed_float_types.all; use ieee_proposed.fixed_pkg.all; use ieee_proposed.float_pkg.all;  entity sigmoid     port (         clk     : in std_logic;         x       : in  float32;         y       : out sfixed(15 downto -16)     ); end sigmoid;  architecture behavioral of sigmoid      signal size : sfixed(15 downto -16);  begin       set_c: process(clk)     begin          if rising_edge(clk)            y <= to_sfixed(x, size);         end if;     end process;  end behavioral; 

from i've been reading on various forums , in documentation, code should synthesize fine. also, fixed float conversion using to_float(fixed) works fine. have missed something? there other simple ways of implementing float -> fixed conversion?

whenever use bishop's library synthesis, include packages in project , declare them following case:

use work.float_pkg.all; use work.fixed_pkg.all; 

i don't use ieee_proposed library.

regarding conversion, believe easiest way use package functions (directly or more 1 type conversion).